Research Interests
- On-chip interconnection networks.
- High performance multicore and distributed computer
architectures.
- Processor memory systems.
Current Publications
- "Asynchronous Bypass Channel Routers: Improving Performance for DVFS
and GALS NoCs," Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, To appear in The 4th ACM/IEEE International Symposium on Networks-on-Chip, May 2010.
- "Ocin_sim - a DVFS aware simulator for NoC based platforms", Subodh Prabhu, Boris Grot, Paul V. Gratz and Jiang Hu. The 1st Workshop on SoC Archtecture, Accelerators and Workloads (SAW-1), January 2010. pdf, website
- "Realistic Workload Characterization and Analysis for Networks-on-Chip Design", Paul V. Gratz and Stephen W. Keckler. The 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), January 2010. pdf
- "Asynchronous Bypass Channel Routers," Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, Technical Report:TAMU-ECE-2009-05, August 24, 2009
- "Evaluation of the TRIPS Computer System," M. Gebhart,
B. A. Maher, K. E. Coons, J. Diamond, P. Gratz, M. Marino,
N. Ranganathan, B. Robatmili, A. Smith, J. Burrill, S. W. Keckler, D.
Burger, K. S. McKinley. The 14th International Conference on
Architectural Support for Programming Languages and Operating Systems
(ASPLOS), March 2009 (Received best paper award).
pdf
- "Regional Congestion Awareness for Load Balance in
Networks-on-Chip," P. Gratz, B. Grot, and S.W. Keckler. The
14th IEEE International Symposium on High-Performance Computer
Architecture (HPCA), February 2008. pdf
- "On-Chip Interconnection Networks of the TRIPS Chip," P. Gratz,
C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, and
D.C. Burger. IEEE Micro, 27(5), pp. 41-50,
September/October 2007. pdf
- "TRIPS: A Distributed Explicit Data Graph Execution (EDGE)
Microprocessor," M.S. Govindan, K. Sankaralingam, R. Nagarajan, R.
McDonald, R. Desikan, S. Drolia, P. Gratz, D. Gulati, H. Hanson,
C.K. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P.
Shivakumar, S.W. Keckler, and D. Burger, HotChips 19,
August 2007.
- "Implementation and Evaluation of a Dynamically Routed Processor
Operand Network," P. Gratz, K. Sankaralingam, H. Hanson,
P. Shivakumar, R. McDonald, S.W. Keckler, and D.C. Burger. The
First IEEE International Symposium on Networks-on-Chips (NOCS),
pp 7 - 17, May, 2007. pdf
- "Distributed Microarchitectural Protocols in the TRIPS Prototype
Processor," K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan,
S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim,
H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P.K. Shivakumar,
S. W. Keckler, D.C. Burger. The 36th IEEE/ACM International
Symposium on Microarchitecture (MICRO), pp. 480 - 491, December
2006. pdf
- "Implementation and Evaluation of On-Chip Network Architectures,"
P. Gratz, C. Kim, R. McDonald, S.W. Keckler, and
D.C. Burger. 2006 IEEE International Conference on Computer
Design (ICCD), pp 477 - 484, October, 2006. pdf
- "Scaling to the End of Silicon with EDGE Architectures," D.C.
Burger, S.W. Keckler, K.S. McKinley, et al. IEEE
Computer, 37 (7), pp. 44-55, July, 2004.pdf
Other Information- Curriculum Vitae
- "Network-On-Chip Implementation and Performance Improvement Through Workload Characterization and Congestion Awareness", P. Gratz, Dissertation, University of Texas at Austin, December 2008. pdf
- A Note to prospective grad students (TBD).
Contact Information Office: 333D WERC
Office Hours: M 3:00-4:00p, W 10:00-11:00a or by appointment
Email: pgratz "at" gratz1.com
Phone: 979-488-4551
Fax: 979-845-2630
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