Paul V. Gratz

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I am an assistant professor in the Department of Electrical and Computer Engineering at the Texas A&M University where I am a member of the Computer Engineering group.

I lead the CAMSIN research group, where our research focuses on security, power, reliability and performance of the future chip-multiprocessor (CMP) and multiprocessor system-on-chip (MPSoC) designs.

I received my PhD in Electrical and Computer Engineering from the University of Texas at Austin, December 2008. On the TRIPS prototype processor project I designed, implemented and verified the second level memory system, on-chip network and chip-to-chip network.

Research Interests

Security, power, reliability and performance in multicore and distributed computer architectures.
Processor memory systems.
On-chip interconnection networks.

Current Publications

"Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router," Y. S. Yang, H. Deshpande, G. Choi and P. V. Gratz. The 2012 IEEE International Symposium on Circuits and Systems (ISCAS), May 2012. (Accepted for publication)
"B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors," Reena Panda , Paul V. Gratz , and Daniel A. Jimenez, IEEE Computer Architecture Letters vol. 99, no. (RapidPosts), 11/29/11. Selected for "Best Papers from IEEE Computer Architecture Letters in 2011"
"An Energy Efﬁcient Datapath for Asymmetric Cryptography," Andrew D. Targhetta and Paul V. Gratz, 3rd Workshop on Energy Efficient Design (WEED 2011), June 2011. pdf, bibtex.
"Asynchronous Bypass Channels for Multi-synchronous NoCs: A Router Microarchitecture, Topology and Routing Algorithm," Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alex Sprintson and Gwan Choi. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, no.11, pp.1663-1676, Nov. 2011. pdf, bibtex.
"Reducing Network-on-Chip Energy Consumption Through Spatial Locality Speculation," Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz and Daniel A. Jimenez. The Fifth ACM/IEEE International Symposium on Networks-on-Chip (NOCS), May 2011. pdf, bibtex.
"AcENoCs: A Conﬁgurable HW/SW Platform for FPGA Accelerated NoC Emulation," Vinayak Pai, Swapnil Lotlikar, Paul Gratz, The 24th IEEE International Conference on VLSI Design (VLSID), January 2011. pdf, bibtex.
"Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect," Hyungjun Kim, Paul Gratz, IEEE Computer Architecture Letters, 9(1), pp.33-36, January 2010. pdf, bibtex.
"Asynchronous Bypass Channel Routers: Improving Performance for DVFS and GALS NoCs," Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, The 4th ACM/IEEE International Symposium on Networks-on-Chip, May 2010. pdf, bibtex.
"Ocin_sim - a DVFS aware simulator for NoC based platforms", Subodh Prabhu, Boris Grot, Paul V. Gratz and Jiang Hu. The 1st Workshop on SoC Archtecture, Accelerators and Workloads (SAW-1), January 2010. pdf , bibtex, website.
"Realistic Workload Characterization and Analysis for Networks-on-Chip Design", Paul V. Gratz and Stephen W. Keckler. The 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects (CMP-MSI), January 2010. pdf, bibtex.
"Running PARSEC 2.1 on M5", Mark Gebhart, Joel Hestness, Ehsan Fatehi, Paul Gratz, Stephen W. Keckler; The University of Texas at Austin, Department of Computer Science. Technical Report #TR-09-32. October 27, 2009. pdf, bibtex, website
"Asynchronous Bypass Channel Routers," Tushar Jain, Paul Gratz, Alex Sprintson, and Gwan Choi, Technical Report:TAMU-ECE-2009-05, August 24, 2009, bibtex.
"Evaluation of the TRIPS Computer System," M. Gebhart, B. A. Maher, K. E. Coons, J. Diamond, P. Gratz, M. Marino, N. Ranganathan, B. Robatmili, A. Smith, J. Burrill, S. W. Keckler, D. Burger, K. S. McKinley. The 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2009 (Received best paper award). pdf, bibtex.
"Regional Congestion Awareness for Load Balance in Networks-on-Chip," P. Gratz, B. Grot, and S.W. Keckler. The 14th IEEE International Symposium on High-Performance Computer Architecture (HPCA), February 2008. pdf, bibtex.
"On-Chip Interconnection Networks of the TRIPS Chip," P. Gratz, C. Kim, K. Sankaralingam, H. Hanson, P. Shivakumar, S.W. Keckler, and D.C. Burger. IEEE Micro, 27(5), pp. 41-50, September/October 2007. pdf, bibtex.
"TRIPS: A Distributed Explicit Data Graph Execution (EDGE) Microprocessor," M.S. Govindan, K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, P. Gratz, D. Gulati, H. Hanson, C.K. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S.W. Keckler, and D. Burger, HotChips 19, August 2007.
"Implementation and Evaluation of a Dynamically Routed Processor Operand Network," P. Gratz, K. Sankaralingam, H. Hanson, P. Shivakumar, R. McDonald, S.W. Keckler, and D.C. Burger. The First IEEE International Symposium on Networks-on-Chips (NOCS), pp 7 - 17, May, 2007. pdf, bibtex.
"Distributed Microarchitectural Protocols in the TRIPS Prototype Processor," K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P.K. Shivakumar, S. W. Keckler, D.C. Burger. The 36th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 480 - 491, December 2006. pdf, bibtex.
"Implementation and Evaluation of On-Chip Network Architectures," P. Gratz, C. Kim, R. McDonald, S.W. Keckler, and D.C. Burger. 2006 IEEE International Conference on Computer Design (ICCD), pp 477 - 484, October, 2006. pdf, bibtex.
"Scaling to the End of Silicon with EDGE Architectures," D.C. Burger, S.W. Keckler, K.S. McKinley, et al. IEEE Computer, 37 (7), pp. 44-55, July, 2004.pdf.

Other Information

Curriculum Vitae
"Network-On-Chip Implementation and Performance Improvement Through Workload Characterization and Congestion Awareness", P. Gratz, Dissertation, University of Texas at Austin, December 2008. pdf
A Note to prospective grad students (TBD).